1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having high adaptability to a high speed bipolar process and formed with a highly integrated transistor array or a diode array, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Even of LSIs, a high speed bipolar device has high speed performance and high current drive capacity as compared with a CMOS device. Therefore, the high speed bipolar device has the edge over an application-specific device. There are known, for example, a laser-driven LSI for optical transmission, a power amplifier for a cellular phone, etc. Also the high speed bipolar device has a high potential in realizing a high-accuracy and a high-sensitive LSI even other than these applications. It can be said that these are similar not only to analog devices but also to digital devices.
Such a bipolar device has a merit toward actualization of various leading-edge devices. Of these, some kind of memory-system device or light-detecting device is capable of bringing out performance unattainable to CMOS by realizing bipolar devices and a highly integrated transistor array or a diode array within the same chip.
A prior art example that realizes such a demand will be explained below. The current typical high-speed bipolar transistor generally adopts an isolation method utilizing LOCOS or a shallow trench and deep trenches in combination. Each of the deep trenches is buried with a CVD oxide film with a view toward minimizing substrate-to-collector capacity.
A schematic sectional structure of a high speed bipolar transistor is shown in FIG. 6(a). A schematic sectional structure of a diode array formed over a semiconductor substrate identical to the bipolar transistor is shown in FIG. 6(b). Further, a schematic plan view at the time that diodes 660 are arranged within the plane in grid form and brought into integration, is shown in FIG. 6(c).
Here, an N+ type buried layer 620 containing As in a high density is formed in a P type silicon substrate 610. An N type epitaxial layer 621 that serves as a collector layer is formed on the N+ type buried layer 620. Deep trenches 630 each buried thereinside with a CVD oxide film are formed in a device isolation region. After etching of the deep trenches 630, boron is ion-implanted to form channel stop layers 635 for enhancing a further isolation effect.
A LOCOS oxide film 640 of about 0.7 m is formed around the N type epitaxial layer 621 to reduce parasitic capacity. Further, according to a self-aligned process, a P type base layer 622 and an N type emitter layer 623 are formed over the N type epitaxial layer 621 from one mask. Thereafter, a collector electrode 651, an emitter electrode 650 and base electrodes 652 that connect the collector layer, emitter layer and base layer respectively are formed on an insulating film 625. A detailed structure of a junction portion will not be explained.
The diode shown in FIG. 6(b) can be formed in a process similar to the self-aligned bipolar transistor shown in FIG. 6(a). Thus, a PN junction diode is configured in which the emitter electrode 650 of the transistor is provided as a cathode 654 and the base electrode 652 is provided as an anode 653. Here, no LOCOS oxide film is formed inside the diode array, and the LOCOS oxide film 641 is formed only outside the diode array. This is because a pattern conversion difference caused by the formation of the LOCOS oxide film is reduced to form a more highly integrated array.
A self-aligned contact method for reducing a parasitic capacitor of a device has been described in a patent document (Japanese Unexamined Patent Publication No. Hei 6(1994)-318600). In order to relax stress in a device isolation trench region, a method of oxidizing a polysilicon film formed within a trench to thereby embed it in the trench has been described in a patent document (Japanese Unexamined Patent Publication No. Hei 9(1997)-172061). A method of forming a polysilicon film before the formation of a CVD silicon film has been described in a patent document (Japanese Unexamined Patent Publication No. 2000-31264). A high withstand and low on-resistance device in which the depth and open width of a trench and the width of a current path region have been defined, has been described in a patent document (Japanese Unexamined Patent Publication No. 2002-164540). Further, a method of preventing the occurrence of a crack without forming a bonding pad over each cross trench has been described in a patent document (Japanese Unexamined Patent Publication No. Hei 10(1998)-135454).
However, in the general method of forming the deep trenches in the device isolation region and burying the deep trenches with the CVD oxide film in the transistors or diode array, a crossed pattern portion C of the deep trenches 630 occurs as shown in FIG. 6(c) and the probability of occurrence of a crystal defect becomes high at the crossed pattern portion of the trenches as distinct from other portions, with the result that yields are reduced. The induced cause of the crystal defect results from going out of stress balance of a trench end with thermal shrinkage in a heat-treating process subsequent to the formation of the CVD oxide film.